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DESCRIPTION
The WM8152 is a 16-bit analogue front end/digitiser IC which processes and digitises the analogue output signals from CCD sensors or Contact Image Sensors (CIS) at pixel sample rates of up to 12MSPS. The device includes a complete analogue signal processing channel containing Reset Level Clamping, Correlated Double Sampling, Programmable Gain and Offset adjust functions. Internal multiplexers allow fast switching of offset and gain for line-by-line colour processing. The output from this channel is time multiplexed into a high-speed 16-bit Analogue to Digital Converter. The digital output data is available in 4-bit wide multiplexed format. An internal 4-bit DAC is supplied for internal reference level generation. This may be used to reference CIS signals or during Reset Level Clamping to clamp CCD signals. An external reference level may also be supplied. ADC references are generated internally, ensuring optimum performance from the device. Using an analogue supply voltage of 5V, a digital core voltage of 5V, and a digital interface supply of either 5V or 3.3V, the WM8152 typically only consumes 225mW when operating from a single 5V supply.
WM8152
Single Channel 16-bit CIS/CCD AFE with 4-bit Wide Output
FEATURES
* * * * * * * * * * * * * 16-bit ADC 12MSPS conversion rate Low power - 225mW typical 5V single supply or 5V/3.3V dual supply operation Single channel operation Correlated double sampling Programmable gain (8-bit resolution) Programmable offset adjust (8-bit resolution) Programmable clamp voltage 4-bit wide multiplexed data output format Internally generated voltage references 20-lead SSOP package Serial control interface
APPLICATIONS
* * * * Flatbed and sheetfeed scanners USB compatible scanners Multi-function peripherals High-performance CCD sensor interface
BLOCK DIAGRAM
VSMP
MCLK
AVDD
DVDD1
DVDD2
VRT VRX VRB
CL
RS VS
TIMING CONTROL
VREF/BIAS
R
M GU X B
8
OFFSET DAC + PGA
8
VINP
RLC
CDS
+ I/P SIGNAL POLARITY ADJUST
16BIT ADC
DATA I/O PORT
OP[0] OP[1] OP[2] OP[3]/SDO
VRLC/VBIAS
R G B M U X
W WM8152
RLC DAC
4
CONFIGURABLE SERIAL CONTROL INTERFACE
SEN SCK SDI
AGND1
AGND2
DGND
WOLFSON MICROELECTRONICS plc
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Production Data, April 2007, Rev 4.2 Copyright (c)2007 Wolfson Microelectronics plc
WM8152 TABLE OF CONTENTS
Production Data
DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 BLOCK DIAGRAM .................................................................................................1 TABLE OF CONTENTS .........................................................................................2 PIN CONFIGURATION...........................................................................................3 ORDERING INFORMATION ..................................................................................3 PIN DESCRIPTION ................................................................................................4 ABSOLUTE MAXIMUM RATINGS.........................................................................5 RECOMMENDED OPERATING CONDITIONS .....................................................5 THERMAL PERFORMANCE .................................................................................5 ELECTRICAL CHARACTERISTICS ......................................................................6
INPUT VIDEO SAMPLING ............................................................................................. 8 OUTPUT DATA TIMING ................................................................................................ 8 SERIAL INTERFACE ..................................................................................................... 9
INTERNAL POWER ON RESET CIRCUIT ..........................................................10 DEVICE DESCRIPTION.......................................................................................12
INTRODUCTION.......................................................................................................... 12 INPUT SAMPLING ....................................................................................................... 12 RESET LEVEL CLAMPING (RLC) ............................................................................... 12 CDS/NON-CDS PROCESSING ................................................................................... 13 OFFSET ADJUST AND PROGRAMMABLE GAIN....................................................... 14 ADC INPUT BLACK LEVEL ADJUST .......................................................................... 15 OVERALL SIGNAL FLOW SUMMARY ........................................................................ 15 CALCULATING OUTPUT FOR ANY GIVEN INPUT .................................................... 15 OUTPUT DATA FORMAT............................................................................................ 17 CONTROL INTERFACE .............................................................................................. 18 TIMING REQUIREMENTS ........................................................................................... 18 PROGRAMMABLE VSMP DETECT CIRCUIT ............................................................. 19 REFERENCES............................................................................................................. 20 POWER SUPPLY ........................................................................................................ 20 POWER MANAGEMENT ............................................................................................. 20 OPERATING MODES .................................................................................................. 20 OPERATING MODE TIMING DIAGRAMS ................................................................... 21
DEVICE CONFIGURATION .................................................................................23
REGISTER MAP .......................................................................................................... 23 REGISTER MAP DESCRIPTION ................................................................................. 24
APPLICATIONS INFORMATION .........................................................................26
RECOMMENDED EXTERNAL COMPONENTS........................................................... 26 RECOMMENDED EXTERNAL COMPONENTS VALUES............................................ 26
PACKAGE DIMENSIONS ....................................................................................27 IMPORTANT NOTICE ..........................................................................................28
ADDRESS:................................................................................................................... 28
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WM8152
PIN CONFIGURATION
AGND2 DVDD1 VSMP MCLK DGND SEN DVDD2 SDI SCK OP[0] 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 VINP VRLC/VBIAS VRX VRT VRB AGND1 AVDD OP[3]/SDO OP[2] OP[1]
WM8152
15 14 13 12 11
ORDERING INFORMATION
DEVICE WM8152SCDS WM8152SCDS/R Note: Reel quantity = 2,000 TEMPERATURE RANGE 0 to 70oC 0 to 70oC PACKAGE 20-lead SSOP (Pb free) 20-lead SSOP (Pb free, tape and reel) MOISTURE SENSITIVITY LEVEL MSL1 MSL1 PEAK SOLDERING TEMPERATURE 260oC 260oC
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WM8152 PIN DESCRIPTION
PIN 1 2 3 4 5 6 7 8 9 NAME AGND2 DVDD1 VSMP MCLK DGND SEN DVDD2 SDI SCK TYPE Supply Supply Digital input Digital input Supply Digital input Supply Digital input Digital input DESCRIPTION Analogue ground (0V). Digital core (logic and clock generator) supply (5V) Video sample synchronisation pulse.
Production Data
Master clock. This clock is applied at N times the input pixel rate (N = 2, 3, 6, 8 or any multiple of 2 thereafter depending on input sample mode). Digital ground (0V). Enables the serial interface when high. Digital supply (5V/3.3V), all digital I/O pins. Serial data input. Serial clock. Digital multiplexed output data bus. ADC output data (d15:d0) is available in 4-bit multiplexed format as shown below. A B d8 d9 d10 d11 C d4 d5 d6 d7 D d0 d1 d2 d3
10 11 12 13
OP[0] OP[1] OP[2] OP[3]/SDO
Digital output Digital output Digital output Digital output
d12 d13 d14 d15
Alternatively, pin OP[3]/SDO may be used to output register read-back data when address bit 4=1 and SEN has been pulsed high. See Serial Interface description in Device Description section for further details. 14 15 16 17 18 19 AVDD AGND1 VRB VRT VRX VRLC/VBIAS Supply Supply Analogue output Analogue output Analogue output Analogue I/O Analogue supply (5V) Analogue ground (0V). Lower reference voltage. This pin must be connected to AGND via a decoupling capacitor. Upper reference voltage. This pin must be connected to AGND via a decoupling capacitor. Input return bias voltage. This pin must be connected to AGND via a decoupling capacitor. Selectable analogue output voltage for RLC or single-ended bias reference. This pin would typically be connected to AGND via a decoupling capacitor. VRLC can be externally driven if programmed Hi-Z. Video input.
20
VINP
Analogue input
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WM8152
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. CONDITION Analogue supply voltage: AVDD Digital core voltage: DVDD1 Digital IO supply voltage: DVDD2 Digital ground: DGND Analogue grounds: AGND1 - 2 Digital inputs, digital outputs and digital I/O pins Analogue input (VINP) Other pins Operating temperature range: TA Storage temperature after soldering Package body temperature (soldering, 10 seconds) Package body temperature (soldering, 2 minutes) Notes: 1. 2. GND denotes the voltage of any ground pin. AGND1, AGND2 and DGND pins are intended to be operated at the same potential. Differential voltages between these pins will degrade performance. MIN GND - 0.3V GND - 0.3V GND - 0.3V GND - 0.3V GND - 0.3V GND - 0.3V GND - 0.3V GND - 0.3V 0C -65C MAX GND + 7V GND + 7V GND + 7V GND + 0.3V GND + 0.3V DVDD2 + 0.3V AVDD + 0.3V AVDD + 0.3V +70C +150C +260C +183C
RECOMMENDED OPERATING CONDITIONS
CONDITION Operating temperature range Analogue supply voltage Digital core supply voltage Digital I/O supply voltage 5V I/O 3.3V I/O SYMBOL TA AVDD DVDD1 DVDD2 DVDD2 MIN 0 4.75 4.75 4.75 2.97 5.0 5.0 5.0 3.3 TYP MAX 70 5.25 5.25 5.25 3.63 UNITS C V V V V
THERMAL PERFORMANCE
PARAMETER Performance Thermal resistance - junction to case Thermal resistance - junction to ambient Notes: 1. Figures given are for package mounted on 4-layer FR4 according to JESD51-5 and JESD51-7. PD Rev 4.2 April 2007 5 RJC RJA Tambient = 25C 32.2 81.1 C/W C/W SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
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WM8152 ELECTRICAL CHARACTERISTICS
Production Data
Test Conditions AVDD = DVDD1 = 5.0V, DVDD2 = 3.3V, AGND = DGND = 0V, TA = 25C, MCLK = 24MHz unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS Max Gain Min Gain VIN Gain = 0dB; PGA[7:0] = 07(hex) Gain = 0dB; PGA[7:0] = 07(hex) DNL INL Min Gain Max Gain VRT VRB VRX VRTB 1.55 1.15 0 -50 -50 10 10 1.25 25 4.5 14 2.70 1.45 1.65 1.25 1 20 1.86 VRLC = 0 to AVDD 4 VRLCSTEP VRLCSTEP VRLCBOT VRLCBOT VRLCTOP VRLCTOP AVDD = 5.0V AVDD = 5.0V AVDD = 5.0V 0.23 0.14 0.34 0.20 4.0 2.56 0.25 0.16 0.39 0.26 4.16 2.66 0.27 0.20 0.44 0.31 4.3 2.76 50 2 2 1 100 4.5 1.75 1.35 MIN TYP MAX UNIT
Overall System Specification (including 16-bit ADC, PGA, Offset and CDS functions) Full-scale input voltage range (see Note 1) Input signal limits (see Note 2) Full-scale transition error Zero-scale transition error Differential non-linearity Integral non-linearity Total output noise References Upper reference voltage Lower reference voltage Input return bias voltage Diff. reference voltage (VRT-VRB) Output resistance VRT, VRB, VRX VRLC/Reset-Level Clamp (RLC) RLC switching impedance VRLC short-circuit current VRLC output resistance VRLC Hi-Z leakage current RLCDAC resolution RLCDAC step size, RLCDAC = 0 RLCDAC step size, RLCDAC = 1 RLCDAC output voltage at code 0(hex), RLCDACRNG = 0 RLCDAC output voltage at code 0(hex), RLCDACRNG = 1 RLCDAC output voltage at code F(hex) RLCDACRNG, = 0 RLCDAC output voltage at code F(hex), RLCDACRNG = 1 Resolution Differential non-linearity Integral non-linearity Step size Output voltage Code 00(hex) Code FF(hex) -247 +247 DNL INL mA A bits V/step V/step V V V V V V V V 0.30 3.22 VDD +50 +50 Vp-p Vp-p V mV mV LSB LSB LSB rms LSB rms
Offset DAC, Monotonicity Guaranteed 8 0.1 0.25 2.04 -260 +260 -273 +273 0.5 1 bits LSB LSB mV/step mV mV
Notes: 1. Full-scale input voltage denotes the peak input signal amplitude that can be gained to match the ADC input range. 2. Input signal limits are the limits within which the full-scale input voltage signal must lie.
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Production Data Test Conditions AVDD = DVDD1 = 5.0V, DVDD2 = 3.3V, AGND = DGND = 0V, TA = 25C, MCLK = 24MHz unless otherwise stated. PARAMETER Programmable Gain Amplifier Resolution Gain equation Max gain Min gain Gain error Internal channel offset Analogue to Digital Converter Resolution Maximum Speed Full-scale input range (2*(VRT-VRB)) DIGITAL SPECIFICATIONS Digital Inputs High level input voltage Low level input voltage High level input current Low level input current Input capacitance Digital Outputs High level output voltage Low level output voltage Supply Currents Total supply current - active Total analogue AVDD, supply current - active Total digital core, DVDD1, supply current - active Digital I/O supply current, DVDD2 - active (see note 3) Supply current - full power down mode Notes: 3. Digital I/O supply current depends on the capacitive load attached to the pin. The Digital I/O supply current is measured with approximately 50pF attached to the pin. IAVDD IDVDD1 IDVDD2 45 41 3 3 300 400 VOH VOL IOH = 1mA IOL = 1mA DVDD2 - 0.5 0.5 VIH VIL IIH IIL CI 5 0.7 DVDD2 VFS 12 2.5 16 VOFF GMAX GMIN 6.8 0.75
0.78 +
WM8152
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
8
PGA[7 : 0] x 7.57 255
bits V/V 8.7 0.82 2 V/V V/V % mV bits MSPS V
8.35 0.78 1 10
V 0.2 DVDD2 1 1 V A A pF V V mA mA mA mA A
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WM8152
INPUT VIDEO SAMPLING
tPER MCLK tVSMPSU VSMP INPUT tVSU VIDEO tVH tRSU tRH tVSMPH tMCLKH tMCLKL
Production Data
Figure 1 Input Video Timing Note: 1. See Page 15 (Programmable VSMP Detect Circuit) for video sampling description.
Test Conditions VDD = 5.0V, DVDD = 3.3V, AGND = DGND = 0V, TA = 25C, MCLK = 24MHz unless otherwise stated. PARAMETER MCLK period MCLK high period MCLK low period VSMP set-up time VSMP hold time Video level set-up time Video level hold time Reset level set-up time Reset level hold time Notes: 1. 2. tVSU and tRSU denote the set-up time required after the input video signal has settled. Parameters are measured at 50% of the rising/falling edge. SYMBOL tPER tMCLKH tMCLKL tVSMPSU tVSMPH tVSU tVH tRSU tRH TEST CONDITIONS MIN 41.6 18.8 18.8 6 3 10 3 10 3 TYP MAX UNITS ns ns ns ns ns ns ns ns ns
OUTPUT DATA TIMING
MCLK tPD tPD
OP[3:0]
Figure 2 Output Data Timing Test Conditions VDD = 5.0V, DVDD = 3.3V, AGND = DGND = 0V, TA = 25C, MCLK = 24MHz unless otherwise stated. PARAMETER Output propagation delay SYMBOL tPD TEST CONDITIONS IOH = 1mA, IOL = 1mA MIN TYP MAX 20 UNITS ns
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WM8152
SERIAL INTERFACE
tSPER SCK tSSU SDI tSCE SEN tSERD ADC DATA SDO MSB REGISTER DATA LSB tSCRD t SCRDZ ADC DATA tSEW tSEC tSH tSCKL tSCKH
Figure 3 Serial Interface Timing Test Conditions VDD = 5.0V, DVDD = 3.3V, AGND = DGND = 0V, TA = 25C, MCLK = 24MHz unless otherwise stated. PARAMETER SCK period SCK high SCK low SDI set-up time SDI hold time SCK to SEN set-up time SEN to SCK set-up time SEN pulse width SEN low to SDO = Register data SCK low to SDO = Register data SCK low to SDO = ADC data Note: 1. Parameters are measured at 50% of the rising/falling edge SYMBOL tSPER tSCKH tSCKL tSSU tSH tSCE tSEC tSEW tSERD tSCRD tSCRDZ TEST CONDITIONS MIN 41.6 18.8 18.8 6 6 12 12 25 30 30 30 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns
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WM8152 INTERNAL POWER ON RESET CIRCUIT
Production Data
Figure 4 Internal Power On Reset Circuit Schematic The WM8152 includes an internal Power-On-Reset Circuit, as shown in Figure 4, which is used to reset the digital logic into a default state after power up. The POR circuit is powered from AVDD and monitors DVDD1. It asserts PORB low if AVDD or DVDD1 is below a minimum threshold. The power supplies can be brought up in any order but is important that either AVDD is brought up and is stable before DVDD comes up or vice versa as shown in Figure 5 and Figure 6.
Figure 5 Typical Power up Sequence where AVDD is Powered before DVDD1
Figure 5 shows a typical power-up sequence where AVDD is powered up first. When AVDD rises above the minimum threshold, Vpora, there is enough voltage for the circuit to guarantee PORB is asserted low and the chip is held in reset. In this condition, all writes to the control interface are ignored. Now AVDD is at full supply level. Next DVDD1 rises to Vpord_on and PORB is released high and all registers are in their default state and writes to the control interface may take place. On power down, where AVDD falls first, PORB is asserted low whenever AVDD drops below the minimum threshold Vpora_off.
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WM8152
Figure 6 Typical Power up Sequence where DVDD1 is Powered before AVDD
Figure 6 shows a typical power-up sequence where DVDD1 is powered up first. It is assumed that DVDD1 is already up to specified operating voltage. When AVDD goes above the minimum threshold, Vpora, there is enough voltage for the circuit to guarantee PORB is asserted low and the chip is held in reset. In this condition, all writes to the control interface are ignored. When AVDD rises to Vpora_on, PORB is released high and all registers are in their default state and writes to the control interface may take place. On power down, where DVDD1 falls first, PORB is asserted low whenever DVDD1 drops below the minimum threshold Vpord_off.
SYMBOL Vpora Vpora_on Vpora_off Vpord_on Vpord_off
TYP 0.6 1.2 0.6 0.7 0.6
UNIT V V V V V
Table 1 Typical POR Operation (typical values, not tested)
Note: It is recommended that every time power is cycled to the WM8199 a software reset is written to the software register to ensure that the contents of the control registers are at their default values before carrying out any other register writes.
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WM8152 DEVICE DESCRIPTION
INTRODUCTION
A block diagram of the device showing the signal path is presented on Page 1.
Production Data
The WM8152 processes the sampled video signal on VINP with respect to the video reset level or an internally/externally generated reference level through the analogue processing channel. This processing channel consists of an Input Sampling block with optional Reset Level Clamping (RLC) and Correlated Double Sampling (CDS), an 8-bit programmable offset DAC and an 8-bit Programmable Gain Amplifier (PGA). The ADC then converts each resulting analogue signal to a 16-bit digital word. The digital output from the ADC is presented on a 4-bit wide bus. On-chip control registers determine the configuration of the device, including the offsets and gains applied to each channel. These registers are programmable via a serial interface.
INPUT SAMPLING
The WM8152 has a single analogue processing channel and ADC which can be used in a flexible manner to process both monochrome and line-by-line colour inputs. Monochrome: VINP is sampled, processed by the analogue channel, and converted by the ADC. The same offset DAC and PGA register values are always applied. Colour Line-by-Line: VINP is sampled and processing by the analogue channel before being converted by the ADC. The gains and offset register values applied to the PGA and offset DAC can be switched between the independent Red, Green and Blue digital registers (e.g. Red Green Blue Red...) at the start of each line in order to facilitate line-by-line colour operation. The INTM[1:0] bits determine which register contents are applied (see Table 2) to the PGA and offset DAC. By using the INTM[1:0] bits to select the desired register values only one register write is required at the start of each new colour line.
RESET LEVEL CLAMPING (RLC)
To ensure that the signal applied to the WM8152 VINP pin lies within the valid input range (0V to VDD) the CCD output signal is usually level shifted by coupling through a capacitor, CIN. When active, the RLC circuit clamps the WM8152 side of this capacitor to a suitable voltage during the CCD reset period. The RLCINT register bit controls is used to activate the Reset Level Clamp circuit. A typical input configuration is shown in Figure 7. The Timing Control Block generates an internal clamp pulse, CL, from MCLK and VSMP (when RLCINT is high). When CL is active the voltage on the WM8152 side of CIN, at VINP, is forced to the VRLC/VBIAS voltage (VVRLC) by closing switch 1. When the CL pulse turns off, switch 1 opens the voltage at VINP initially remains at VVRLC but any subsequent variation in sensor voltage (from reset to video level) will couple through CIN to VINP. RLC is compatible with both CDS and non-CDS operating modes, as selected by switch 2. Refer to the CDS/non-CDS Processing section.
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Production Data
WM8152
MCLK VSMP
TIMING CONTROL CL RS VS
FROM CONTROL INTERFACE
CIN
S/H +
VINP 1
RLC
2
+
S/H INPUT SAMPLING BLOCK
TO OFFSET DAC
CDS
EXTERNAL VRLC VRLC/ VBIAS
4-BIT RLC DAC VRLCEXT
CDS
FROM CONTROL INTERFACE
Figure 7 Reset Level Clamping and CDS Circuitry Reset Level Clamping is controlled by register bit RLCINT. Figure 8 illustrates the effect of the RLCINT bit for a typical CCD waveform, with CL applied during the reset period. The RLCINT register bit is sampled on the positive edge of MCLK that occurs during each VSMP pulse. The sampled level, high (or low) controls the presence (or absence) of the internal CL pulse on the next reset level. The position of CL can be adjusted by using control bits CDSREF[1:0] (Figure 9).
MCLK
VSMP
ACYC/RLC or RLCINT
1
X Programmable Delay
X
0
X
X
0
CL (CDSREF = 01)
INPUT VIDEO
RGB
RGB RLC on this Pixel
RGB No RLC on this Pixel
Figure 8 Relationship of RLCINT, MCLK and VSMP to Internal Clamp Pulse, CL The VRLC/VBIAS pin can be driven internally by a 4-bit DAC (RLCDAC) by writing to control bits RLCV[3:0]. The RLCDAC range and step size may be increased by writing to control bit RLCDACRNG. Alternatively, the VRLC/VBIAS pin can be driven externally by writing to control bit VRLCEXT to disable the RLCDAC and then applying a d.c. voltage to the pin.
CDS/NON-CDS PROCESSING
For CCD type input signals, the signal may be processed using CDS, which will remove pixel-by-pixel common mode noise. For CDS operation, the video level is processed with respect to the video reset level, regardless of whether RLC has been performed. To sample using CDS, control bit CDS must be set to 1 (default), this sets switch 2 into the position shown in (Figure 7) and causes the signal reference to come from the video reset level. The time at which the reset level is sampled, by clock Rs/CL, is adjustable by programming control bits CDSREF[1:0], as shown in Figure 9.
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WM8152
Production Data
MCLK VSMP
VS RS/CL (CDSREF = 00) RS/CL (CDSREF = 01) RS/CL (CDSREF = 10) RS/CL (CDSREF = 11)
Figure 9 Reset Sample and Clamp Timing For CIS type sensor signals, non-CDS processing is used. In this case, the video level is processed with respect to the voltage on pin VRLC/VBIAS, generated internally or externally as described above. The VRLC/VBIAS pin is sampled by Rs at the same time as Vs samples the video level in this mode; non-CDS processing is achieved by setting switch 2 in the lower position, CDS = 0.
OFFSET ADJUST AND PROGRAMMABLE GAIN
The output from the CDS block is a differential signal, which is added to the output of an 8-bit Offset DAC to compensate for offsets and then amplified by an 8-bit PGA. The gain and offset can be set for each of three colours by writing to control bits DACx[7:0] and PGAx[7:0] (where x can be R, G or B). In colour line-by-line mode the gain and offset coefficients that are applied to the PGA and offset DAC can be multiplexed by control of the INTM[1:0] bits as shown in Table 2. INTM[1:0] 00 01 10 11 DESCRIPTION Red offset and gain registers are applied to offset DAC and PGA (DACR[7:0] and PGAR[7:0]) Green offset and gain registers applied to offset DAC and PGA (DACG[7:0] and PGAG[7:0]) Blue offset and gain registers applied to offset DAC and PGA (DACB[7:0] and PGAB[7:0]) Reserved.
Table 2 Offset DAC and PGA Register Control The gain characteristic of the WM8152 PGA is shown in Figure 10. Figure 11 shows the maximum input voltage (at VINP) that can be gained up to match the ADC full-scale input range (2.5V).
9 8 7 PGA GAIN V/V 6 5 4 3 2 1 0 0 64 128 192 256 GAIN REGISTER VALUE, PGA[7:0]
3.5 3 2.5 2 1.5 1 0.5 0 0 64 128 192 256 GAIN REGISTER VALUE, PGA[7:0]
Figure 10 PGA Gain Characteristic
Figure 11 Peak Input Voltage to Match ADC Full-scale
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PEAK INPUT VOLTAGE TO MATCH ADC FULL-SCALE RANGE
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WM8152
Range
ADC INPUT BLACK LEVEL ADJUST
The output from the PGA should be offset to match the full-scale range of the ADC (VFS = 2.5V). For negative-going input video signals, a black level (zero differential) output from the PGA should be offset to the top of the ADC range by setting register bits PGAFS[1:0]=10. For positive going input signal the black level should be offset to the bottom of the ADC range by setting PGAFS[1:0]=11. Bipolar input video is accommodated by setting PGAFS[1:0]=00 or PGAFS[1:0]=01 (zero differential input voltage gives mid-range ADC output).
OVERALL SIGNAL FLOW SUMMARY
Figure 12 represents the processing of the video signal through the WM8152.
OUTPUT INVERT BLOCK
INPUT SAMPLING OFFSET DAC PGA BLOCK BLOCK BLOCK
ADC BLOCK
V1
VIN CDS = 1 VRESET CDS = 0 VVRLC VRLCEXT=1 VRLCEXT=0
V2
++
V3
+
-
X
analog
x (65535/VFS) +0 if PGAFS[1:0]=11 +65535 if PGAFS[1:0]=10 +32767 if PGAFS[1:0]=0x
D1
digital
D2
OP[3:0]
D2 = D1 if INVOP = 0 D2 =65535-D1 if INVOP = 1 PGA gain A = 0.78+(PGA[7:0]*7.57)/255
Offset DAC
260mV*(DAC[7:0]-127.5)/127.5
VIN is VINP voltage sampled on video sample VRESET is VINP sampled during reset clamp VVRLC is voltage applied to VRLC pin CDS, VRLCEXT,RLCV[3:0], DAC[7:0], PGA[7:0], PGAFS[1:0] and INVOP are set by programming internal control registers. CDS=1 for CDS, 0 for non-CDS
RLC DAC
VRLCSTEP*RLCV[3:0] + VRLCBOT
Figure 12 Overall Signal Flow
The INPUT SAMPLING BLOCK produces an effective input voltage V1. For CDS, this is the difference between the input video level VIN and the input reset level VRESET. For non-CDS this is the difference between the input video level VIN and the voltage on the VRLC/VBIAS pin, VVRLC, optionally set via the RLC DAC. The OFFSET DAC BLOCK then adds the amount of fine offset adjustment required to move the black level of the input signal towards 0V, producing V2. The PGA BLOCK then amplifies the white level of the input signal to maximise the ADC range, outputting voltage V3. The ADC BLOCK then converts the analogue signal, V3, to a 16-bit unsigned digital output, D1. The digital output is then inverted, if required, through the OUTPUT INVERT BLOCK to produce D2.
CALCULATING OUTPUT FOR ANY GIVEN INPUT
The following equations describe the processing of the video and reset level signals through the WM8152. The values of V1 V2 and V3 are often calculated in reverse order during device setup. The PGA value is written first to set the input Voltage range, the Offset DAC is then adjusted to compensate for any Black/Reset level offsets and finally the RLC DAC value is set to position the reset level correctly during operation. Note: Refer to WAN0123 for detailed information on device calibration procedures.
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WM8152
INPUT SAMPLING BLOCK: INPUT SAMPLING AND REFERENCING
Production Data
If CDS = 1, (i.e. CDS operation) the previously sampled reset level, VRESET, is subtracted from the input video. V1 = VIN - VRESET ................................................................... Eqn. 1
If CDS = 0, (non-CDS operation) the simultaneously sampled voltage on pin VRLC is subtracted instead. V1 = VIN - VVRLC .................................................................... Eqn. 2
If VRLCEXT = 1, VVRLC is an externally applied voltage on pin VRLC/VBIAS. If VRLCEXT = 0, VVRLC is the output from the internal RLC DAC. VVRLC = (VRLCSTEP RLCV[3:0]) + VRLCBOT ................................. Eqn. 3
VRLCSTEP is the step size of the RLC DAC and VRLCBOT is the minimum output of the RLC DAC.
OFFSET DAC BLOCK: OFFSET (BLACK-LEVEL) ADJUST
The resultant signal V1 is added to the Offset DAC output. V2 = V1 + {260mV (DAC[7:0]-127.5) } / 127.5 ..................... Eqn. 4
PGA NODE: GAIN ADJUST
The signal is then multiplied by the PGA gain, V3 = V2 [0.78+(PGA[7:0]*7.57)/255] ................................... Eqn. 5
ADC BLOCK: ANALOGUE-DIGITAL CONVERSION
The analogue signal is then converted to a 16-bit unsigned number, with input range configured by PGAFS[1:0]. D1[15:0] = INT{ (V3 /VFS) 65535} + 32767 PGAFS[1:0] = 00 or 01 ...... D1[15:0] = INT{ (V3 /VFS) 65535} PGAFS[1:0] = 11 ............... Eqn. 6 Eqn. 7 Eqn. 8
D1[15:0] = INT{ (V3 /VFS) 65535} + 65535 PGAFS[1:0] = 10 ............... where the ADC full-scale range, VFS = 2.5V if D1[15:0] < 0 D1[15:0] = 0
if D1[15:0] > 65535 D1[15:0] = 65535
OUTPUT INVERT BLOCK: POLARITY ADJUST
The polarity of the digital output may be inverted by control bit INVOP. D2[15:0] = D1[15:0] D2[15:0] = 65535 - D1[15:0] (INVOP = 0) ...................... (INVOP = 1) ...................... Eqn. 9 Eqn. 10
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WM8152
OUTPUT DATA FORMAT
The digital data output from the ADC is available to the user in 4-bit wide multiplexed. Latency of valid output data with respect to VSMP is programmable by writing to control bits DEL[1:0]. The latency for each mode is shown in the Operating Mode Timing Diagrams section. Figure 13 shows the output data formats for Mode 1 and 3 - 6. Figure 14 shows the output data formats for Mode 2. Table 3 summarises the output data obtained for each format.
MCLK
MCLK 4+4+4+4-BIT OUTPUT
4+4+4+4-BIT OUTPUT
A
B
C
D
ABABCD
Figure 13 Output Data Formats (Modes 1, 3, 4) OUTPUT FORMAT 4+4+4+4-bit (nibble) OUTPUT PINS OP[3:0]
Figure 14 Output Data Formats (Mode 2) OUTPUT
A = d15, d14, d13, d12 B = d11, d10, d9, d8 C = d7, d6, d5, d4 D = d3, d2, d1, d0
Table 3 Details of Output Data Shown in Figure 13 and Figure 14
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WM8152
CONTROL INTERFACE
Production Data
The internal control registers are programmable via the serial digital control interface. The register contents can be read back via the serial interface on pin OP[3]/SDO. Note: It is recommended that a software reset is carried out after the power-up sequence, before writing to any other register. This ensures that all registers are set to their default values (as shown in Table 5).
SERIAL INTERFACE: REGISTER WRITE
Figure 15 shows register writing in serial mode. Three pins, SCK, SDI and SEN are used. A six-bit address (a5, 0, a3, a2, a1, a0) is clocked in through SDI, MSB first, followed by an eight-bit data word (b7, b6, b5, b4, b3, b2, b1, b0), also MSB first. Each bit is latched on the rising edge of SCK. When the data has been shifted into the device, a pulse is applied to SEN to transfer the data to the appropriate internal register. Note all valid registers have address bit a4 equal to 0 in write mode.
SCK
SDI
a5
0
a3
a2
a1
a0
b7
b6
b5
b4
b3
b2
b1
b0
Address SEN
Data Word
Figure 15 Serial Interface Register Write A software reset is carried out by writing to Address "000100" with any value of data, (i.e. Data Word = XXXXXXXX.
SERIAL INTERFACE: REGISTER READ-BACK
Figure 16 shows register read-back in serial mode. Read-back is initiated by writing to the serial bus as described above but with address bit a4 set to 1, followed by an 8-bit dummy data word. Writing address (a5, 1, a3, a2, a1, a0) will cause the contents (d7, d6, d5, d4, d3, d2, d1, d0) of corresponding register (a5, 0, a3, a2, a1, a0) to be output MSB first on pin SDO (on the falling edge of SCK). Note that pin SDO is shared with an output pin, OP[3], so no data can be read when reading from a register. The next word may be read in to SDI while the previous word is still being output on SDO.
SCK
SDI
a5
1 a3 a2 a1 a0
x
x
x
x
x
x
x
x
Address SEN
Data Word
SDO
d7 d6 d5 d4 d3 d2 d1 d0
Output Data Word
Figure 16 Serial Interface Register Read-back
TIMING REQUIREMENTS
To use this device a master clock (MCLK) of up to 24MHz and a per-pixel synchronisation clock (VSMP) of up to 12MHz are required. These clocks drive a timing control block, which produces internal signals to control the sampling of the video signal. MCLK to VSMP ratios and maximum sample rates for the various modes are shown in Table 4.
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WM8152
PROGRAMMABLE VSMP DETECT CIRCUIT
The VSMP input is used to determine the sampling point and frequency of the WM8152. Under normal operation a pulse of 1 MCLK period should be applied to VSMP at the desired sampling frequency (as shown in the Operating Mode Timing Diagrams) and the input sample will be taken on the first rising MCLK edge after VSMP has gone low. However, in certain applications such a signal may not be readily available. The programmable VSMP detect circuit in the WM8152 allows the sampling point to be derived from any signal of the correct frequency, such as a CCD shift register clock, when applied to the VSMP pin. When enabled, by setting the VSMPDET control bit, the circuit detects either a rising or falling edge (determined by POSNNEG control bit) on the VSMP input pin and generates an internal VSMP pulse. This pulse can optionally be delayed by a number of MCLK periods, specified by the VDEL[2:0] bits. Figure 17 shows the internal VSMP pulses that can be generated by this circuit for a typical clock input signal. The internal VSMP pulse is then applied to the timing control block in place of the normal VSMP pulse provided from the input pin. The sampling point then occurs on the first rising MCLK edge after this internal VSMP pulse, as shown in the Operating Mode Timing Diagrams.
MCLK INPUT PINS VSMP POSNNEG = 1 (VDEL = 000) INTVSMP (VDEL = 001) INTVSMP (VDEL = 010) INTVSMP (VDEL = 011) INTVSMP (VDEL = 100) INTVSMP (VDEL = 101) INTVSMP (VDEL = 110) INTVSMP (VDEL = 111) INTVSMP POSNNEG = 0 (VDEL = 000) INTVSMP (VDEL = 001) INTVSMP (VDEL = 010) INTVSMP (VDEL = 011) INTVSMP (VDEL = 100) INTVSMP (VDEL = 101) INTVSMP (VDEL = 110) INTVSMP (VDEL = 111) INTVSMP
VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS
Figure 17 Internal VSMP Pulses Generated by Programmable VSMP Detect Circuit
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WM8152
REFERENCES
Production Data
The ADC reference voltages are derived from an internal bandgap reference, and buffered to pins VRT and VRB, where they must be decoupled to ground. Pin VRX is driven by a similar buffer, and also requires decoupling. The output buffer from the RLCDAC also requires decoupling at pin VRLC/VBIAS when this is configured as an output.
POWER SUPPLY
The WM8152 can run from a 5V single supply or from split 5V (core) and 3.3V (digital interface) supplies.
POWER MANAGEMENT
Power management for the device is performed via the Control Interface. The device can be powered on or off completely by setting the EN bit low. All the internal registers maintain their previously programmed value in power down mode and the Control Interface inputs remain active.
OPERATING MODES
Table 4 summarises the most commonly used modes, the clock waveforms required and the register contents required for CDS and non-CDS operation.
MODE
DESCRIPTION
CDS AVAILABLE Yes
MAX SAMPLE RATE 4MSPS
TIMING REQUIREMENTS MCLK max = 24MHz MCLK:VSMP ratio is 6:1 MCLK max = 24MHz MCLK:VSMP ratio is 3:1 MCLK max = 24MHz MCLK:VSMP ratio is 2:1 MCLK max = 24MHz MCLK:VSMP ratio is 2n:1, n 4
REGISTER CONTENTS WITH CDS SetReg1: 0F(hex)
REGISTER CONTENTS WITHOUT CDS SetReg1: 0D(hex)
1
Monochrome/ Colour Line-by-Line Fast Monochrome/ Colour Line-by-Line
2
Yes
8MSPS
Identical to Mode 1 plus SetReg3: bits 5:4 must be set to 0(hex) CDS not possible
Identical to Mode 1
3
Maximum speed Monochrome/ Colour Line-by-Line Slow Monochrome/ Colour Line-by-Line
No
12MSPS
SetReg1: 4D(hex)
4
Yes
3MSPS
Identical to Mode 1
Identical to Mode 1
Table 4 WM8152 Operating Modes
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WM8152
OPERATING MODE TIMING DIAGRAMS
The following diagrams show 4-bit multiplexed output data and MCLK, VSMP and input video requirements for operation of the most commonly used modes as shown in Table 4. The diagrams are identical for both CDS and non-CDS operation.
16.5 MCLK PERIODS MCLK VSMP
VINP OP[3:0] (DEL = 00) OP[3:0] (DEL = 01) OP[3:0] (DEL = 10) OP[3:0] (DEL = 11)
ABC ABC D ABC D ABC D ABC D ABCD
D
ABC
D
ABC
D
ABC
D
ABC
D
D
ABC
D
ABC
D
ABC
D
ABC
D
D
ABC
D
ABC
D
ABC
D
ABCD
Figure 18 Mode 1 Operation
23.5 MCLK PERIODS MCLK VSMP
VINP OP[3:0] (DEL = 00) OP[3:0] (DEL = 01) OP[3:0] (DEL = 10) OP[3:0] (DEL = 11)
CDABABCDABABCDABABCDABABCDABABCDABABCDABABCDABABCDABABCDABABCDABABCDABABCD
CDABABCDABABCDAB AB CDABABCDABABCDABABCDABABCDABABCDABABCDABAB CDABABCDABABCD
CDABABCDA BABCDABABCDABABCDABABCDABABCDA BABCDABAB CDA BABCDAB AB CDABABCDABABCD
CDABABCDABABCDABABCDABABCDABABCDABABCDABABCDABABCDABABCDABABCDABABCDABABCD
Figure 19 Mode 2 Operation
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WM8152
16.5 MCLK PERIODS
Production Data
MCLK VSMP VINP OP[3:0] (DEL = 00) OP[3:0] (DEL = 01) OP[3:0] (DEL = 10) OP[3:0] (DEL = 11)
ABCDABCDABCDABCDABCDABCDABCDABCDABCDABCDABCDABCDABCD
ABCDABCDABCDABCDABCDABCDABCDABCDABCDABCDABCDABCDABCD
ABCDABCDABCDABCDABCDABCDABCDABCDABCDABCDABCDABCDABCD
ABCDABCDABCDABCDABCDABCDABCDABCDABCDABCDABCDABCDABCD
Figure 20 Mode 3 Operation
16.5 MCLK PERIODS
MCLK VSMP
VINP OP[3:0] (DEL = 00) OP[3:0] (DEL = 01) OP[3:0] (DEL = 10) OP[3:0] (DEL = 11)
ABC D ABC D ABC D ABC D
D
ABC
D
ABC
D
ABC
D
D
ABC
D
ABC
D
ABC
D
D
ABC
D
ABC
D
ABCD
Figure 21 Mode 4 Operation (MCLK:VSMP Ratio = 8:1)
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WM8152
DEVICE CONFIGURATION
REGISTER MAP
The following table describes the location of each control bit used to determine the operation of the WM8152. The register map is programmed by writing the required codes to the appropriate addresses via the serial interface.
ADDRESS 000001 000010 000011 000100 000110 000111 001000 001001 001010 001011 001100 100000 100001 100010 100011 101000 101001 101010 101011
DESCRIPTION
DEF (hex)
RW b7 RW RW RW W RW R RW RW RW RW RW RW RW RW W RW RW RW W 0 0 0 TCLK 0 0 0 DACR[7]
DACG[7]
BIT b6 MODE3 DEL[0] 0 b5 PGAFS[1] RLCDACRNG CDSREF [1] b4 PGAFS[0] 0 CDSREF [0] b3 1 VRLCEXT RLCV[3] b2 1 INVOP RLCV[2] b1 CDS 1 RLCV[1] b0 EN 1 RLCV[0]
Setup Reg 1 Setup Reg 2 Setup Reg 3 Software Reset Setup Reg 4 Revision Number Setup Reg 5 Test Reg 1 Reserved Reserved Reserved DAC Value (Red) DAC Value (Green) DAC Value (Blue) DAC Value (RGB) PGA Gain (Red) PGA Gain (Green) PGA Gain (Blue) PGA Gain (RGB)
0F 23 1F 00 05 41 00 00 00 00 00 80 80 80 80 00 00 00 00
0 DEL[1] 0
0 1 0 0 0 0 0 DACR[6]
DACG[6]
INTM[1] 0 0 0 0 0 0 DACR[5] DACG[5] DACB[5] DAC[5] PGAR[5] PGAG[5] PGAB[5] PGA[5]
INTM[0] 0 POSNNEG 0 0 0 0 DACR[4] DACG[4] DACB[4] DAC[4] PGAR[4] PGAG[4] PGAB[4] PGA[4]
RLCINT 0 VDEL[2] 0 0 0 0 DACR[3] DACG[3] DACB[3] DAC[3] PGAR[3] PGAG[3] PGAB[3] PGA[3]
1 0 VDEL[1] 0 0 0 0 DACR[2] DACG[2] DACB[2] DAC[2] PGAR[2] PGAG[2] PGAB[2] PGA[2]
0 0 VDEL[0] 0 0 0 0 DACR[1] DACG[1] DACB[1] DAC[1] PGAR[1] PGAG[1] PGAB[1] PGA[1]
1 1 VSMPDET 0 0 0 0 DACR[0] DACG[0] DACB[0] DAC[0] PGAR[0] PGAG[0] PGAB[0] PGA[0]
DACB[7] DAC[7] PGAR[7]
PGAG[7]
DACB[6] DAC[6] PGAR[6]
PGAG[6]
PGAB[7] PGA[7]
PGAB[6] PGA[6]
Table 5 Register Map
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WM8152
REGISTER MAP DESCRIPTION
Production Data
The following table describes the function of each of the control bits shown in Table 5. REGISTER Setup Register 1 BIT NO 0 1 3:2 5:4 BIT NAME(S) EN CDS Reserved PGAFS[1:0] DEFAULT 1 1 11 00 DESCRIPTION 0 = complete power down, 1 = fully active. Select correlated double sampling mode: 0 = single ended mode, 1 = CDS mode. Must be set to one Offsets PGA output to optimise the ADC range for different polarity sensor output signals. Zero differential PGA input signal gives: 00 = Zero output (use for bipolar video) 01 = Zero output 6 7 Setup Register 2 1:0 2 MODE3 Reserved Reserved INVOP 0 0 11 0 10 = Full-scale positive output (use for negative going video) 11 = Full-scale negative output (use for positive going video)
Required when operating in MODE3: 0 = other modes, 1 = MODE3. Must be set to zero Must be set to one Digitally inverts the polarity of output data. 0 = negative going video gives negative going output, 1 = negative-going video gives positive going output data. When set powers down the RLCDAC, changing its output to Hi-Z, allowing VRLC/VBIAS to be externally driven. Must be set to zero Sets the output range of the RLCDAC. 0 = RLCDAC ranges from 0 to VDD (approximately), 1 = RLCDAC ranges from 0 to VRT (approximately). Sets the output latency in ADC clock periods. 1 ADC clock period = 2 MCLK periods except in Mode 2 where 1 ADC clock period = 3 MCLK periods. 00 = Minimum latency 01 = Delay by one ADC clock period 10 = Delay by two ADC clock periods 11 = Delay by three ADC clock periods
3 4 5
VRLCEXT Reserved RLCDACRNG
0 0 1
7:6
DEL[1:0]
00
Setup Register 3
3:0
RLCV[3:0]
1111
Controls RLCDAC driving VRLC pin to define single ended signal reference voltage or Reset Level Clamp voltage. See Electrical Characteristics section for ranges. CDS mode reset timing adjust. 00 = Advance 1 MCLK period 01 = Normal 10 = Retard 1 MCLK period 11 = Retard 2 MCLK periods
5:4
CDSREF[1:0]
01
7:6 Software Reset Setup Register 4 2:0 3 5:4
Reserved
00
Must be set to zero Any write to Software Reset causes all cells to be reset. It is recommended that a software reset be performed after a power-up before any other register writes.
Reserved RLCINT INTM[1:0]
101 0 00
Must be set to 101 This bit is used to determine whether Reset Level Clamping is enabled. 0 = RLC disabled, 1 = RLC enabled. Colour selection bits used in internal modes. 00 = Red, 01 = Green, 10 = Blue and 11 = Reserved. See Table 2 for details. Must be set to zero
7:6
Reserved
00
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Production Data REGISTER Setup Register 5 BIT NO 0 BIT NAME(S) VSMPDET DEFAULT 0 DESCRIPTION
WM8152
0 = Normal operation, signal on VSMP input pin is applied directly to Timing Control block. 1 = Programmable VSMP detect circuit is enabled. An internal synchronisation pulse is generated from signal applied to VSMP input pin and is applied to Timing Control block. When VSMPDET = 0 these bits have no effect. When VSMPDET = 1 these bits set a programmable delay from the detected edge of the signal applied to the VSMP pin. The internally generated pulse is delayed by VDEL MCLK periods from the detected edge. See Figure 17, Internal VSMP Pulses Generated for details. When VSMPDET = 0 this bit has no effect. When VSMPDET = 1 this bit controls whether positive or negative edges are detected: 0 = Negative edge on VSMP pin is detected and used to generate internal timing pulse. 1 = Positive edge on VSMP pin is detected and used to generate internal timing pulse. See Figure 17 for further details. Must be set to zero 0 = Normal Operation, OP[3:0] output ADC data. 1 = Internal Clock Test Mode. This allows internal timing signals to be multiplexed onto the OP[3:0] pins as follows. PIN OP[3] OP[2] OP[1] OP[0] TCLK=0 OP[3] OP[2] OP[1] OP[0] TCLK=1 INTVSMP Video sample clock ADC clock Reset sample clock
3:1
VDEL[2:0]
000
4
POSNNEG
0
7:5 Test Register 1 7
Reserved TCLK
000 0
Offset DAC (Red) Offset DAC (Green) Offset DAC (Blue) Offset DAC (RGB) PGA gain (Red) PGA gain (Green) PGA gain (Blue) PGA gain (RGB)
7:0 7:0 7:0 7:0 7:0
DACR[7:0] DACG[7:0] DACB[7:0] DAC[7:0] PGAR[7:0]
10000000 10000000 10000000
Red channel offset DAC value. Used under control of the INTM[1:0] control bits. Green channel offset DAC value. Used under control of the INTM[1:0] control bits. Blue channel offset DAC value. Used under control of the INTM[1:0] control bits. A write to this register location causes the red, green and blue offset DAC registers to be overwritten by the new value
00000000
Determines the gain of the red channel PGA according to the equation: Red channel PGA gain = [0.78+(PGAR[7:0]*7.57)/255]. Used under control of the INTM[1:0] control bits. Determines the gain of the green channel PGA according to the equation: Green channel PGA gain = [0.78+(PGAG[7:0]*7.57)/255]. Used under control of the INTM[1:0] control bits. Determines the gain of the blue channel PGA according to the equation: Blue channel PGA gain = [0.78+(PGAB[7:0]*7.57)/255]. Used under control of the INTM[1:0] control bits. A write to this register location causes the red, green and blue PGA gain registers to be overwritten by the new value
7:0
PGAG[7:0]
00000000
7:0
PGAB[7:0]
00000000
7:0
PGA[7:0]
Table 6 Register Control Bits
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WM8152 APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
DVDD2 DVDD1
Production Data
DVDD2 DVDD1 C1 C2 AVDD AVDD C3 DGND DGND
DGND
AGND1 AGND2 AGND
AGND
Video Input
VRT VINP VRX VRB C6 C7 C8 C4 C5
WM8152
VRLC/VBIAS C9
AGND
AGND DVDD2 MCLK DVDD1 + C11 AVDD + C12
Timing Signals
VSMP
+ C10 OP[3]/SDO
SCK
OP[2] OP[1] OP[0]
Interface Controls
SDI SEN
Output Data Bus
DGND
DGND
AGND
NOTES: 1. C1-9 should be fitted as close to WM8152 as possible. 2. AGND and DGND should be connected as close to WM8152 as possible.
Figure 22 External Components Diagram
RECOMMENDED EXTERNAL COMPONENTS VALUES
COMPONENT REFERENCE C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 SUGGESTED VALUE 100nF 100nF 100nF 10nF 1F 100nF 100nF 100nF 100nF 10F 10F 10F DESCRIPTION De-coupling for DVDD2. De-coupling for DVDD1. De-coupling for AVDD. High frequency de-coupling between VRT and VRB. Low frequency de-coupling between VRT and VRB (non-polarised). De-coupling for VRB. De-coupling for VRX. De-coupling for VRT. De-coupling for VRLC. Reservoir capacitor for DVDD2. Reservoir capacitor for DVDD1. Reservoir capacitor for AVDD.
Table 7 External Components Descriptions
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Production Data
WM8152
PACKAGE DIMENSIONS
DS: 20 PIN SSOP (7.2 x 5.3 x 1.75 mm) DM0015.C
b
20
e
11
E1
E
1
10
GAUGE PLANE
D
A A2
A1 -C0.10 C
SEATING PLANE
c
L L1
0.25
Symbols A A1 A2 b c D e E E1 L L1 REF: MIN ----0.05 1.65 0.22 0.09 6.90 7.40 5.00 0.55 0
o
Dimensions (mm) NOM --------1.75 0.30 ----7.20 0.65 BSC 7.80 5.30 0.75 1.25 REF o 4 JEDEC.95, MO -150
MAX 2.0 ----1.85 0.38 0.25 7.50 8.20 5.60 0.95 8
o
NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM. D. MEETS JEDEC.95 MO-150, VARIATION = AE. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
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PD Rev 4.2 April 2007 27
WM8152 IMPORTANT NOTICE
Production Data
Wolfson Microelectronics plc ("Wolfson") products and services are sold subject to Wolfson's terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement.
Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current.
Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty. Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation.
In order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product.
Wolfson's products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. Any use of products by the customer for such purposes is at the customer's own risk.
Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. Any provision or publication of any third party's products or services does not constitute Wolfson's approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner.
Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon.
Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in Wolfson's standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person's own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person.
ADDRESS:
Wolfson Microelectronics plc 20 Bernard Terrace Edinburgh EH8 9NX United Kingdom
Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com
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